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RM0008
12.5.12
Digital-to-analog converter (DAC)
DAC channel1 data output register (DAC_DOR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DACC1DOR[11:0]
Reserved
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:12 Reserved.
Bit 11:0 DACC1DOR[11:0] : DAC channel1 data output
These bits are read only, they contain data output for DAC channel1.
12.5.13
DAC channel2 data output register (DAC_DOR2)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DACC2DOR[11:0]
Reserved
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:12 Reserved.
Bit 11:0 DACC2DOR[11:0] : DAC channel2 data output
These bits are read only, they contain data output for DAC channel2.
Doc ID 13902 Rev 9
251/995
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